Hey! I'm Bhushan

I am currently pursuing my Master’s in Computer Engineering at Texas A&M University, where I am building a strong foundation in advanced semiconductor design methodologies. The rigorous coursework, combined with hands-on project experience, has significantly strengthened my understanding the technical concepts. Applying these concepts has enhanced my skills and tremendously added to my prior work experience. I am eager to contribute to cutting-edge projects where precision, scalability, and innovation define success. I am confident that my technical expertise, problem-solving mindset, and leadership qualities will enable me to add value to the industry.


INTERESTED IN THE FOLLOWING ROLES

  • Physical Design
  • SoC Design Verification
VIEW RESUME
Bhushan Kiran Munoli

Education

work Texas A&M University

MS in Electrical and Computer Engineering

August 2025 - May 2027

  • Fall 2025
    • CSCE 614: Computer Architecture
    • CSCE 616: Introduction to Hardware Design Verification
    • ECEN 714: Digital Integrated Circuit Design
  • Spring 2026
    • CSCE 714: Advanced Hardware Design Functional Verification
    • ECEN 676: Advanced Computer Architecture
    • ECEN 749: Microprocessor Systems Design

work PES University

B.Tech in Electronics and Computer Engineering

August 2019 - May 2023

  • Relevant Courses
    • Computer Organization and Digital Design
    • Digital VLSI Design
    • Digital Design using Verilog: ASIC and FPGA Cadence Tool
    • Verification of Digital Systems
    • Analog Circuit Design
    • Control Systems
    • Machine Learning
    • Artificial Neural Networks
View Degree Certificate View Transcript

Work Experience

work Maven Silicon

ASIC Physical Design Engineer

Mar 2025 - Dec 2025 (India - Remote)

  • Built Net-list to GDS II design flow of RISC-V for a 32nm design with constraint files, along with analysis of area, power & time tradeoff. Performed placement, routing for macros and standard cells along with Concurrent Clock and Data Optimization and Integrated Clock Gating
  • Performed Static Timing Analysis and Clock Tree Synthesis to manage timing delays for a 5ns clock. Analyzed timing reports for input and output delay constraints. Worked on Clock domain Crossing to manage clocks of different frequencies.
  • Achieved standard cell and core area reduction to 29338.9μm2 and total power reduction, minimizing congestion and meeting setup time and hold time requirements

work Deloitte India

SAP SuccessFactors Consultant & CPI Developer

Jul 2023 - Jul 2025 (India - Onsite)

  • SAP SuccessFactors Consultant SAP Cloud Platform Integration (CPI):
    • Created integration suites from scratch to send messages from Happay, S/4HANA, LinkedIn, IIM Jobs, Secure, Docusign, Adobe Acrobat etc. to SAP SuccessFactors.
    • Built test scripts and iFlows for custom and standard integrations using Groovy Script and Java Script.
    • Performed Odata API integrations and SFTP based integration with SAP BASIS and SAP SF solutions.
    • Conducted client workshops and pre-sales workshops to boost sales and build customer relations
  • SAP SuccessFactors Recruitment Management:
    • Collaborated with various clients to conduct client workshops and successfully implemented the Recruitment Management and Recruitment Marketing modules of SAP SuccessFactors according to the customer needs.
    • Being a part of the project management team, I have handled more than 5 different SAP Modules at the same time and have resolve over 500 support tickets for all the modules combined, consistently meeting service level agreements (SLAs) and deadlines.
    • Integrated the RCM module to various modules like Performance and Goal Management, S/4 HANA for seamless data transfer.
  • SAP SuccessFactors Onboarding 2.0:
    • Implementation of the ONB2.0 system from scratch for clients in India, USA, UAE, and Bangladesh seamlessly connecting the system to the DBMS- S/4 HANA and Employee Central.
    • Conducted client workshops to analyze the new developments in technology and how the business can utilize it to improve their day to day functions. This required me to utilize various contacts at SAP to analyze the developments.
    • Integrated the RCM module to various modules like Performance and Goal Management, S/4 HANA for seamless data transfer.
    Experience Letter

    work Zebra Technologies

    Network Engineer (Intern)

    Jan 2023 - July 2023 (India - Onsite)

    • Worked on test automation scripts, creating them from scratch solving bugs in the existing ones mainly using Robot Framework and python.
    • The testing was conducted on WLAN devices to check for WIFI and Bluetooth connectivity.
    • Developed system apps for WLAN devices to verify Wi-Fi and Bluetooth connectivity using Java and Python and concepts of Bluetooth Low energy and time synchronization improving device testing
    • Collaborated with cross-functional teams to reduced the system time difference between the devices to 2 milliseconds by sending a modified NTP packet from the host server and test 4+ devices simultaneously
    Internship Completion Certificate

    Computer Architecture Projects, Texas A&M University

    Implementation of Cache Replacement and Insertion Policies Across L3 Cache Sizes

    Nov 2025 - Dec 2025

    Implemented and Analyzed SRRIP, iTP, xPTP, iTP-xPTP, CPSD and L-Hybrid Cache Replacement and Cahce Insertion policies for 1mb, 2mb 4mb and 8mb cache sizes in ZSIM simulator. Executed various benchmarks to test the policies' performance for single thread, multi-thread, integer and floating point instructions.

    Branch Predictor Implementation

    Sept 2025 - Oct 2025

    Implemented Adaptive Branch Predictors with the reference of the research "Alternative Implementations of Two-Level Adaptive Branch Prediction". Simulated the models on ZSIM simulator and obtained 97% branch prediction accuracy.

    Hardware Design Verification Projects, Texas A&M University

    Functional Verification of Hyper Transport Advanced X-Bar

    Aug 2025 - Dec 2025

    Created a verification plan using vManager to review and track the functional specifications of HTAX. Set up the verification environment by developing and integrating UVM test-bench components including assertions, cover points, drivers, and monitors. Ran random sequence regression and performed root cause analysis to achieve 100% coverage.

    Router 1x3 Implementation

    Mar 2025 - Jul 2025

    Used Verilog, System Verilog, and UVM along with Synopsys VCS and Xilinx Vivado to build a UVM-based test-bench with sequence items, driver, monitor, and scoreboard. Executed regression testing with randomized sequences and debugged failures to reach full functional coverage.

    Physical Design Projects, Texas A&M University

    Implementation of Random Double Bit and Burst ECC for HBM3

    Aug 2025 - Inprogress

    Designed RTL level error correction code. Tested the design on a FPGA board. Developed a Matlab script to analyze results. Building a design on 180nm technology to meet the SoC specification with 21.27% reduction in area

    Design of Pipelined Adder with Buffered H-clock Tree

    Aug 2025 - Dec 2025

    Worked on designing and analyzing schematics and layouts for NAND, XOR, and NOT logic gates, along with flip-flop and SRAM circuits. Developed transistor-level schematics and layouts for an 8-bit pipelined adder with a buffered H-clock tree. Used the logical effort method to optimize transistor sizing, which resulted in a 33% reduction in delay.

    Logic Synthesis & STA of Cruise Control System

    Oct 2025 - Nov 2025

    Built a 5-state Verilog-based cruise control FSM with 20 D flip-flops, implementing acceleration and braking control logic, and synthesized it using Cadence Genus. Identified the top 3 critical setup and hold paths through static timing analysis and achieved signoff-level closure with zero timing violations.

    RISC-V Implementation

    Mar 2025 - Oct 2025

    Built a 32-bit microprocessor (RISC-V core) from RTL to GDSII using 32nm technology. Performed full Clock Tree Synthesis, to optimize clock distribution and minimize skew. Performed Macro, Standard cell placement & congestion analysis. Completed placement and post route optimization. Optimized the design to operate reliably at a clock period of 5ns with an area of 29338.9μm2

    Router 1x3 Implementation

    Mar 2025 - Jul 2025

    Designed a Router 1x3 using 32nm technology with L Shaped floor-planning and 333MHz clock frequency. Performed full Clock Tree Synthesis and initialized DRC check to correct violations in the router design

    Undergraduate Projects at PES University, India

    Implementation of IoT-Based Healthcare Kit

    Jan 2022 - May 2023

    View Research Paper

    Human Voice Analysis to Determine Age and Gender

    Aug 2023 - Dec 2023

    View Research Paper

    Professional Cadence Certifications

    System Verilog for Design and Verification v25.03

    System Verilog for Design and Verification

    System Verilog Assertions v5.2

    System Verilog Assertions

    Jasper Formal Fundamentals v25.09

    Jasper Formal Fundamentals

    Basic Static Timing Analysis v3.0

    Basic Static Timing Analysis

    Skills

    SoC Design Verification
    • UVM
    • System Verilog & Verilog
    • Protocols
      • Advanced Microcontroller Bus Architecture(AMBA)
      • Hyper Transport Advanced X-Bar (HTAX)
      • Universal Serial Bus (USB)
      • Inter-Integrated Circuit (I2C)
      • Universal Asynchronous Receiver/Transmitter (UART)
    • GPU & CPU Architecture
    • Softwares
      • Cadence vManager
      • Xcelium
      • SimVision
      • IMC
    ASIC Physical Design
    • Floor-Planning
    • Placement & Routing
    • Static Timings Analysis
    • Clock Tree Analysis
    • Power Analysis
    • TCL Scripting
    • Perl
    • Softwares
      • Cadence
        • Virtuoso
        • Spectre
      • Synopsys
        • Design Compiler
        • Fusion Compiler
        • IC Compiler
        • Prime Time
    Programming
    • C
    • C++
    • Verilog
    • System Verilog
    • Python
    • Make file
    • Linux Shell
    • Git

    Contact

    Currently in College Station, Texas, United States of America.

    bhushanmunolijobsearch@gmail.com +1(979)-344-6100 Bhushan Kiran Munoli GitHub